For years, the semiconductor race was largely about making transistors smaller. That contest is far from over, but the AI boom has shifted part of the battleground elsewhere: how multiple chips are assembled, connected and kept reliable inside a single package.
That is the problem Synopsys and Singapore’s Agency for Science, Technology and Research (A*STAR) are now trying to address.
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The US-based chip design software company and Singapore’s national research agency have signed a memorandum of understanding to jointly develop advanced semiconductor-packaging and simulation technologies for artificial intelligence and high-performance computing.
The collaboration will focus on advanced packaging and chiplet-based designs. Chiplets are smaller specialised chips that can be combined in one package to function like a larger, more powerful system. Instead of relying on one monolithic chip to do everything, companies can mix and match computing, memory, networking and other functions in a more modular way.
This approach is increasingly important for AI and high-performance computing, where systems need far more processing power, memory bandwidth and energy efficiency than traditional chip designs can easily deliver. But it also creates new engineering challenges. When several chips are packed tightly together, heat, stress, warping and material behaviour become harder to predict.
Synopsys said digital modelling can help assess how a package is likely to perform before companies spend time and money on physical prototypes. In an industry where development cycles are long and fabrication mistakes are expensive, being able to simulate reliability early can make a meaningful difference.
Why packaging now matters as much as design
The collaboration will run through the ASTAR IME-Ansys Joint Innovation Consortium for Semiconductor Excellence, involving ASTAR’s Institute of Microelectronics and Ansys, which is now part of Synopsys. The consortium will act as a platform for companies and researchers to conduct joint research on advanced System-in-Package technologies.
System-in-Package, or SiP, refers to the integration of multiple chips or components inside one package. It is already used in areas such as smartphones, automotive electronics and wearables, but AI computing is pushing the technology to far greater levels of complexity.
The initial phase of the consortium’s work will focus on mechanical design, modelling and analysis. The partners aim to examine issues including package and wafer warping, thermo-mechanical stress, solder-joint reliability and moisture-induced failures in multi-chiplet designs.
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These may sound like back-end engineering details, but they are central to whether future AI systems can be manufactured at scale. A high-performance chip package may fail if it bends during production, develops microscopic cracks under heat, or suffers from unreliable solder joints over time. For AI data centres, autonomous systems, advanced manufacturing and next-generation consumer electronics, reliability is not optional.
ASTAR IME will lead the consortium’s research, drawing on its semiconductor packaging capabilities and research platforms. Synopsys will provide trial licences to its Ansys simulation software to ASTAR IME and up to 10 member companies. The consortium also plans to explore projects with universities and offer technical training.
That training element is particularly relevant for Singapore and the wider region. Semiconductor ecosystems are not built only on fabs and equipment; they also require engineers who understand materials, design, thermal behaviour, electronics, manufacturing constraints and simulation tools.
Singapore’s semiconductor bet
Singapore has long played an outsized role in the global semiconductor supply chain. It is home to wafer fabrication, assembly and test operations, equipment suppliers, materials companies and regional headquarters for multinational chip firms. While it does not compete with Taiwan or South Korea in leading-edge logic manufacturing, it has positioned itself as a serious hub for specialty chips, advanced packaging, research and manufacturing services.
That positioning matters as the global chip industry becomes more geopolitically fragmented. The United States, China, Europe, Japan, South Korea and Taiwan are all investing heavily in semiconductor capabilities, driven by AI demand and concerns over supply chain resilience. Southeast Asia, meanwhile, has become more important as companies diversify manufacturing footprints and look for politically stable, technically capable locations.
Malaysia is already a major assembly and testing hub, particularly in Penang. Vietnam is attracting interest in chip design and back-end manufacturing. Thailand and the Philippines have existing electronics manufacturing bases. Singapore’s advantage lies in its research institutions, talent base, intellectual-property protections and proximity to both global companies and regional manufacturing networks.
The Synopsys-A*STAR partnership fits neatly into that strategy. Rather than trying to win every part of the chip supply chain, Singapore has been focusing on areas where deep engineering, industry collaboration and applied research can create defensible value.
Terence Gan, Executive Director of A*STAR IME, said advanced packaging is becoming a critical differentiator in chip innovation as systems grow more complex and AI-driven. He added that the collaboration can reinforce Singapore’s position as a semiconductor innovation hub.
Simulation becomes a strategic layer
For Synopsys, the tie-up also reflects how electronic design automation companies are expanding beyond traditional chip design software. The company’s acquisition of Ansys brought simulation capabilities closer to chip and system design, at a time when the boundaries between semiconductor design, packaging and system-level engineering are blurring.
In AI hardware, performance is no longer determined only by the processor. Memory access, interconnects, power delivery, cooling and package architecture all shape the final system. This makes simulation more strategic. Companies need to understand how a design will behave electrically, mechanically and thermally before it reaches production.
Sukhwan Moon, Synopsys Vice President of Asia-Pacific Sales, said the collaboration can support local companies in reliability, performance and scalability, while helping speed time-to-market for AI and high-performance computing technologies.
That time-to-market pressure is intense. AI infrastructure demand has created a rush for more powerful chips, faster networking and more efficient computing systems. Cloud providers, hyperscalers, chip startups and electronics manufacturers are all trying to move quickly, but the hardware cycle remains unforgiving. Mistakes in design or packaging can delay products by months.
The competitive landscape
Synopsys operates in a highly concentrated but fiercely competitive market. Its main global rivals include Cadence Design Systems and Siemens EDA, which also provide chip design, verification and electronic design automation tools. In simulation and engineering software, the enlarged Synopsys now overlaps with companies such as Keysight Technologies, Altair and Dassault Systèmes in certain areas, depending on the application.
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In advanced packaging, competition is not limited to software. Foundries, outsourced semiconductor assembly and test players, and integrated device manufacturers are all building capabilities around chiplets, 2.5D and 3D packaging. TSMC, Intel, Samsung, ASE, Amkor and JCET are among the companies shaping this market globally. For Southeast Asia, this creates both opportunity and pressure: the region can capture more value, but only if it moves beyond low-cost manufacturing into higher-value engineering and research.
A small MoU in a much larger race
The MoU between Synopsys and A*STAR is not a chip factory announcement, nor does it come with the headline-grabbing capital expenditure often associated with semiconductor projects. Its importance lies elsewhere.
Advanced packaging is becoming one of the key ways the chip industry keeps improving performance as traditional scaling becomes harder and more expensive. For AI, where demand for computing power continues to surge, the ability to design reliable multi-chip systems could determine which companies and countries capture the next wave of value.
For Singapore, the partnership strengthens a role it has been cultivating for years: a neutral, research-driven and industry-connected node in the global semiconductor network. For Southeast Asia, it is another sign that the region’s chip opportunity is widening beyond assembly lines.
The future of AI hardware will not be decided only in data centres or wafer fabs. It will also be shaped in the less visible world of packaging labs, simulation platforms and reliability testing — precisely where this collaboration intends to operate.
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